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53 general purpose I/O lines
Input Module
Xiilnx FPGA Part #XC6VLX75T-2FFG784C
Write leveling
Micron Technology DRAM SDRAM-DDR4, Part #: MT44K32M18RB-107E:B TR | Dynamic random access memory | DEX microchip technology 53 general purpose I/O linesMicron Technology DRAM RLDRAM3, Part #: MT44K32M18RB 107E: B TR features: 1066 MHz DDR operation (2133 Mb s ball data rate) 76. 8 Gb s peak bandwidth (x36 at 1066 MHz clock frequency) Organization 32 Meg x 18, and 16 Meg x 36 common I O (CIO) 16 banks 1. 2V center terminated push pull I O 2. 5V VEXT, 1. 35V VDD, 1. 2V VDDQ I O Reduced cycle time (t RC (MIN) = 7. 5 12ns) SDR addressing Programmable READ WRITE latency (RL WL) and burst length Data mask
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